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8308/8306 preliminary product specification subject to change 1 99/10/26 realtek 8/6-port 10/100 mbps ethernet switch controller with embedded memory the rtl8308/8306 chip is a 128-pin low cost and ultra low power consumption 8/6-port 10/100m ethernet switch controller integrated both with a 2m bits embedded dram as packet buffer and a 16k entries of address table. the rtl8308 supports reduced mii (rmii) interface. only single 50mhz oscillator is needed in a switch system to save your bill of material. in addition, the rtl8308/8306 provides a led display specially to indicate a network loop existence. 1. features n support eight/six 10/100mbps ethernet ports with rmii interface n provided non-blocking and non-head-of-line- blocking forwarding n 50mhz 2m bits dram is built in as packet storage buffer. page based buffer management to efficiently utilize the internal packet buffer n ultra low power consumption with less than 180ma at 3.3v operating voltage n embedded 16k entries of look-up table and 128 entries of cam n support address hashing or direct mapping for look-up table. 128-entry cam is used to eliminate the hash collision problem n support full and half duplex operations n link, speed and duplex status are auto- detected via mdio n flow control fully supported: l half-duplex: back pressure l full-duplex: ieee 802.3x n auto-negotiated full-duplex flow control by writing the ability via mdio to external phy n support store-and-forward and cut-through n provide a led display especially to indicate a network loop existence n broadcast storm control n reversible phyad order for diverse phy n 24c02 interface n 128-pin pqfp, 0.35 um, 3.3v cmos technology www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 2 99/10/26 2. general description the rtl8308/8306 provides eight/six 10/100 mbps rmii ethernet ports. each port can operate in 10 mbps or 100 mbps data rate, and in full or half duplex mode. speed, duplex and link status can be acquired by periodically polling the status of the phy devices via mdio. 2m ( or 32k x 64 ) bits, or 256k bytes dram operating in 50mhz clock is built-in as packet storage buffer. to efficiently utilize the packet buffer, the rtl8308/8306 divides the 256k bytes dram into 1k pages of storage spaces, i.e., per page contains 256 bytes. for ethernet packets, the maximum of seven pages are used and the minimum is one. address loo k -up table consists of two spaces. one is a 16k entries of hash table and another is a 128 entries of cam. the rtl8308/8306 uses address hashing algorithm or direct mapping method to search destination mac address and record source mac address from and to the hash table. if hashed or mapped location is not empty , the rtl8308/8306 will compare the destination mac address with the contents of the cam for address searching and store source mac address to cam for learning. the rtl8308/8306 supports ieee 802.3x full duplex flow control and half duplex back pressure congestion control. the ieee 802.3x flow control's ability is auto-negotiated between remote device and the rtl8308/8306 by writing the flow control ability via mdio to external connected phy and restart the auto-negotiation process. for half duplex, the rtl8308/8306 adopts a special back pressure design, forwarding one packet successfully after 28 force collisions, to avoid the connected repeater being partitioned due to lots of collisions. the full /half duplex flow control ability can be enable or disable via enfctrl pin . the rtl8308 provides reversible phyad order feature to connect diverse external phy devices via eeprom's setting. but 8306 doesn't support this function. the rtl8308/8306 is capable to auto-detect the network loop (or bridge loop). when a loop is detected, the loop led is displayed. this capability can be enabled or disabled via enloop pin. the rtl8308/8306 supports non-blocking 148800 packet s /second wire speed forwarding rate and special design to resolve the head-of-line-blocking problem. the rtl8308/8306 can enable broadcast storm control via e nbrdctrl pin. each port will drop www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 3 99/10/26 broadcast packet (did is ff ff ff ff ff ff) after receiving continuous 64 broadcast packets. the counter will be reset as 0 every 800ms or when receiving any non-broadcast packet(did is not ff ff ff ff ff ff) . the rtl8308/8306 uses 2-wire 24c02 interface to access external serial eeprom. www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 4 99/10/26 3. block diagram 8 ports r mii rmii phy eeprom led management i/f i/f 10/ 100 10 /100 i/f mac mac edoram packet i/ f buffer rxfifo txfifo space fifos, queue , dma flow engine tx start addr . control, queue rx/ tx page rx/tx f.p.p. f.p.p. pointer fifos fifo switching space logic flow control 16k-entry address table address-lookup 128-entry address cam engine f.p.p buffer fifo manager www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 5 99/10/26 4. functional description reset after power on reset, the rtl8308/8306 will determine some features from enfctrl, enbrdctrl and enloop pins, auto-load the content of 24c02 serial eeprom, and write abilities to connected phy management registers via mdc/mdio. it is most important that the rtl8308/8306 and connected phys have to use the same reset signal source. otherwise, it is not guaranteed to work properly. rmii interface the rtl8308/8306 provides 10/100 mbps low pin count rmii interface for use between phy and rtl8308/8306. the rmii is capable of supporting 10mbps and 100mbps data rates. a single clock reference, 50mhz, sourced from an external clock input is used for receive and transmit. it also provides independent 2 bit wide ( di-bit) transmit and receive data paths. as the refclk is 10 times the data rate in 10mbps mode each data di-bit must be output on txd[1:0] and input on rxd[1:0] for ten consecutive refclk cycles. the rtl8308/8306 can regenerate the col signal of the mii internally by anding txen and crs as recovered from crsdv. note that txen cannot be anded directly with crsdv since crsdv may toggle at the end of the frame to provide separation of rxdv and crs. rmii specification signals are as below, signal name direction (with respect to the phy) direction (with respect to the rtl8308/8306) use refclk input input synchronous clock reference for receive, transmit and control interface. crsdv output input carrier sense/receive data valid rxd[1:0] output input receive date txen input output transmit enable txd[1:0] input output transmit data serial management interface mdc/mdio the rtl8308/8306 supports phy management through the serial mdio and mdc signal lines. after power on reset, the rtl8308/8306 write abilities to the advertisement register 4 of connected phy and restart the auto-negotiation process through mdio using phy address increasingly from 01000b to 01111b. after restarting auto-negotiation, the rtl8308/8306 will continuously poll the link status and link partner's ability which including speed, duplex and flow control of the phy devices via mdio. the following is the management frame format www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 6 99/10/26 management frame fields pre st op phyad regad ta data idle read 1 ? 1 01 10 aaaaa rrrrr z0 dddddddddddddddd z write 1 ? 1 01 01 aaaaa rrrrr 10 dddddddddddddddd z reversible phyad order the rtl8308 provides the reversible phyad order feature to connect diverse external phy devices. the addresses of port [a] till [h] are corresponding to phyad 01000b till 01111b or to phyad 01111b till 01000b depending on the value of phyad_rv in eeprom. but RTL8306 does not support this feature. address search and learning the rtl8308/8306 supports address hashing or direct mapping algorithm to search destination mac address and learn source mac address. the aging time of the learnt source mac address is 300 seconds or 5 minutes. the either mode can be selected via 24c02. address hashing mode when a packet is receiving, firstly the rtl8308/8306 hashes the destination mac address to get a location index to the 16k-entry hash table and at the same time compares the destination mac address with the contents of the 128-entry cam. if the hash indexed location is valid or the cam comparison is match, this receiving packet will be forwarded to the corresponding destination port. otherwise, the rtl8308/8306 broadcasts the packet. next the rtl8308/8306 hashes the source mac address to get a location index to the hash table, if the hash indexed location has been occupied , i.e., hash collision occurs, the new source mac address will be relocated into the 128-entry cam accordingly. using this eliminates the hash collision problem. address direct mapping mode in this mode, the rtl8308/8306 uses the last 14 bits of sequence number of mac to index to the 16k- entry look-up table. buffer management the embedded dram is divided into two parts. one is packet buffer space for storing received packet data and the other is page pointer space managed by buffer manager. the packet buffer space consists of about 1k storage units in page. each page is comprised of a 8-byte header information, including next page pointer and receive byte count, and 248 bytes of data. the page pointers are contained in page pointer space www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 7 99/10/26 2m bits dram packet buffer space (about 1k pages) page pointer space buffer manager the buffer manager of the rtl8308/8306 contains a free page pointer fifo pool to store and provide available free page pointers to all ports. after power up reset, the buffer manager will initiate descriptor read command to get some available free page pointers from page pointer space. when the content of the fifo is almost empty due to continuous data receptions, the descriptor read command will be reinitiated to get more available free page pointers. in the other hand, when the fifo contents is almost full due to continuous successfully data transmissions, the rtl8308/8306 initiates the descriptor write command to write the additional available free page pointers back to page pointers space. data reception each port contains a receive data fifo and a receive free page pointer fifo. initially the free page pointer fifo is filled up with free page pointers getting from buffer manager. once a packet is coming, the receive data flows into receive data fifo first and then is moved into packet buffer by receive dma engine using the free page pointers in receive free page pointer fifo via get free page command. the rtl8308/8306 always attempts to fill the free page pointer fifo up with free page pointers. data forwarding each port also contains a transmit data fifo, a transmit free page pointer fifo and a transmit start address queue. once a forwarding condition is met, for cut through mode 384 bytes data are received ok or for store-and-forward mode a packet is received completely, the receiving port will pass the beginning page pointer using send tx descriptor command to transmit port and start the transmit dma. the transmission port stores the beginning page pointer in transmit head point queue. the transmit dma moves data from packet buffer through transmit data fifo and to mii or rmii interface using the free page pointer in the transmit free page pointer fifo. once the packet has been forwarded successfully, the rtl8308/8306 uses put free page command to put related free page pointers back to buffer manager's free page pointer fifo. www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 8 99/10/26 flow control the rtl8308/8306 supports ieee 802.3x full duplex flow control and half duplex back pressure congestion control. the ieee 802.3x flow control's ability is auto-negotiated between remote device and the rtl8308/8306 by writing the flow control ability via mdio to external connected phy. the rtl8308/8306 adopts a special back pressure design, forwarding one packet successfully after 28 force collisions, to avoid the connected repeater being partitioned. loop detection the rtl8308/8306 periodically sends out a broadcast 64-byte packet every 3~5 minutes and automatically detect whether if there is a network loop (or bridge loop) existence. the loop led asserted low to indicate there is a loop exits. the led goes out by unplugging the both rtl8308/8306's ports of the loop . the loop frame length is 64 bytes and its format is as below, ffffff sid 0040 0000000 ? 0000 crc head-of-line blocking the rtl8308/8306 incorporate a simple mechanism to prevent head-of -line blocking problem. when a packet receiving from receive port a is destined to a congested port b, this packet will be asked to pause for full duplex or be back pressured for half duplex. if a new packet immediately following this packet is coming to the same receive port a , it is destined to loosely traffic port c rather than the congested port b. then this new packet will be successfully forwarded to port c not affected by port b. the head-of-line blocking problem usually occurs when interconnected between switch and repeater. 24c02 interface the 24c02 interface is a 2-wire serial eeprom interface providing 2k bits storage space. after power on reset, the rtl8308/8306 uses random read and sequential read commands to auto-load configuration settings, switch ethernet id and so on. after auto-loaded, the 24c02 interface pins scl and sda are tri-stated for on-line updating 24c02 contents through a parallel port. 8308/8306 24c02 sclk sclk sda sda parallel port www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 9 99/10/26 24c02 device operation clock and data transitions: the sda pin is normally pulled high with an external register. data on the sda pin may change only during scl low time periods. data changes during scl high periods will indicate a start or stop condition as defined below. start condition : a high-to-low transition of sda with scl high is a start condition which must precede any other command. stop condition : a low-to-high transition of sda with scl high is a stop condition. acknowledge : all addresses and data words are serially transmitted to and from the eeprom in 8 bit words. the 24c02 sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle. random read : a random read requires a "dummy" byte write sequence to load in the data word address. sequential read : for rtl8308/8306, the sequential reads are initiated by a random address read. after the 24c02 receives a data word, it responds with an acknowledge. as long as the 24c02 receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. * start and stop definition sda scl start stop * output acknowledge scl 1 8 9 data in data out start acknowledge www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 10 99/10/26 * random read device word device address address n address sda data n dummy write * sequential read device address sda data n data n+1 data n+x 5. pin assignment start write read stop start r/w ack ack ack no ack read ack ack stop r/w ack no ack ack ack www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 11 99/10/26 111 gnd 119 sysclk 121 sclk 122 sda 123 nc 125 nc 2 nc 3 nc 5 nc 12 rxd1[a] 102 nc 101 gnd 99 nc 98 rxd1[h] 97 rxd0[h] 96 crsdvh] 95 vcc 94 txd1[h] 93 txd0[h] 92 txe[h] 91 rxd1[g] 90 rxd0[g] 89 crsdv[g] 87 txd0[g] 86 txe[g] 85 vcc 84 nc rtl8308 103 vcc 104 nc 105 gnd 106 test 109 vcc 112 enfctrl 116 gnd 117 encuthr 124 vcc 127 nc 128 vcc 1 nc 4 nc 6 gnd 7 txe[a] 8 txd0[a] 9 txd1[a] 10 crsdv[a] 11 rxd0[a] 13 txe[b] 14 txd0[b] 15 txd1[b] 16 vcc 17 vcc 18 crsdv[b] 19 rxd0[b] 38 nc 37 nc 36 gnd 35 gnd 34 gnd 33 nc 32 nc 31 rxd1[c] 30 gnd 29 rxd0[c] 28 crsdv[c] 27 txd1[c] 26 txd0[c] 25 vcc 24 txe[c] 23 gnd 22 gnd 21 gnd 20 rxd1[b] 39 vcc 40 vcc 41 nc 42 nc 43 mdc 44 mdio 45 nc 46 nc 47 refclk 48 gnd 49 gnd 50 nc 51 vcc 52 vcc 53 rst# 54 loopled# 55 nc 56 dramfail 57 nc 58 txe[d] 59 txd0[d] 60 txd1[d] 61 crsdv[d] 62 rxd0[d] 63 rxd1[d] 64 gnd 65 nc 66 vcc 67 nc 68 txe[e] 69 txd0[e] 70 txd1[e] 71 gnd 72 crsdv[e] 73 rxd0[e] 74 rxd1[e] 75 gnd 76 txe[f] 77 txd0[f] 78 txd1[f] 79 crsdv[f] 80 rxd0[f] 81 rxd1[f] 82 gnd 83 gnd 100 nc 88 txd1[g] 107 enbrdctrl 108 enloop 113 vcc 114 nc 115 gnd 118 nc 120 nc 126 gnd 110 nc www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 12 99/10/26 111 gnd 119 sysclk 121 sclk 122 sda 123 nc 125 nc 2 nc 3 nc 5 nc 12 rxd1[a] 102 nc 101 gnd 99 nc 98 gnd 97 gnd 96 gnd 95 vcc 94 nc 93 nc 92 nc 91 gnd 90 gnd 89 gnd 87 nc 86 nc 85 vcc 84 nc RTL8306 103 vcc 104 nc 105 gnd 106 test 109 vcc 112 enfctrl 116 gnd 117 encuthr 124 vcc 127 nc 128 vcc 1 nc 4 nc 6 gnd 7 txe[a] 8 txd0[a] 9 txd1[a] 10 crsdv[a] 11 rxd0[a] 13 txe[b] 14 txd0[b] 15 txd1[b] 16 vcc 17 vcc 18 crsdv[b] 19 rxd0[b] 38 nc 37 nc 36 gnd 35 gnd 34 gnd 33 nc 32 nc 31 rxd1[c] 30 gnd 29 rxd0[c] 28 crsdv[c] 27 txd1[c] 26 txd0[c] 25 vcc 24 txe[c] 23 gnd 22 gnd 21 gnd 20 rxd1[b] 39 vcc 40 vcc 41 nc 42 nc 43 mdc 44 mdio 45 nc 46 nc 47 refclk 48 gnd 49 gnd 50 nc 51 vcc 52 vcc 53 rst# 54 loopled# 55 nc 56 dramfail 57 nc 58 txe[d] 59 txd0[d] 60 txd1[d] 61 crsdv[d] 62 rxd0[d] 63 rxd1[d] 64 gnd 65 nc 66 vcc 67 nc 68 txe[e] 69 txd0[e] 70 txd1[e] 71 gnd 72 crsdv[e] 73 rxd0[e] 74 rxd1[e] 75 gnd 76 txe[f] 77 txd0[f] 78 txd1[f] 79 crsdv[f] 80 rxd0[f] 81 rxd1[f] 82 gnd 83 gnd 100 nc 88 nc 107 enbrdctrl 108 enloop 113 vcc 114 nc 115 gnd 118 nc 120 nc 126 gnd 110 nc www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 13 99/10/26 6.pin descriptions - 8308 pin description rmii interface symbol type pin no description txe[a:h] o 7,13,24,58, 68,76,86,92 transmit enable. the rtl8308 asserts high to indicate that valid data for transmission is presented on the txd[1:0] txd[0:1][a], txd[0:1][b], txd[0:1][c], txd[0:1][d], txd[0:1][e], txd[0:1][f], txd[0:1][g], txd[0:1][h] o 8,9, 14,15, 26,27, 59,60, 69,70, 77,78, 87,88, 93,94 transmit data [1:0]. crsdv[a:h] i 10,18,28,61, 72,79,89,96 crsdv signals. crsdv from phy device is asserted high when media is non-idle. rxd[0:1][a], rxd[0:1][b], rxd[0:1][c], rxd[0:1][d], rxd[0:1][e], rxd[0:1][f], rxd[0:1][g], rxd[0:1][h] i 11,12, 19,20, 29,31, 62,63, 73,74, 80,81, 90,91, 97,98 receive data [1:0]. the rtl8308/8306 captures the receive data on the rising edge of refclk when crsdv is high. refclk i 47 reference clock input. a 50 mhz signal is used for rmii clock reference. mdc o 43 management data clock mdio i/o 44 management data input/output serial eeprom 24c02 interface symbol type pin no description sclk o 121 serial clock: internally pulled high sda i/o 122 serial data input/output: internally pulled high system pins symbol type pin no description rst# i 53 reset: active low to a known reset state. after power-on reset (low to high), the configuration modes from mode pins are determined, the content of serial eeprom is auto- loaded into and the rtl8308/8306 begins to access the management data of phy devices. sysclk i 119 system clock input 50 mhz system clock is used. mode pins (reset-read) symbol type pin no description enloop i 108 enable loop detection: when pulled high upon reset, the auto loop detection is enabled. when pulled low upon reset, it is disabled. www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 14 99/10/26 encuthr i 117 enable cut-through: pulled high upon reset will select the cut-through mode. pulled low upon reset selects the store-and-forward mode. e nbrdctrl i 107 enable broadcast storm control. enfctrl i 112 enable full duplex flow control: pulled high upon reset will enable the full duplex ieee802.3x flow control function. the flow control ability will be write to the management register 4 of phy device one and only one time after power-on reset, for advertising. pulled low upon reset will disable the flow control function. led pin symbol type pin no description loopled# o 54 loop detected led: low active asserted low indicates that a network loop is detected. dramfail o 56 dram fail led: high active asserted high indicates that the embedded dram is failed. test pin symbol type pin no description test i 106 test pin : for internal use must be tied to ground for normal use. power ground pin gnd 6,21,22,23,30,34, 35,36,48,49,64,71, 75,82,83,101,105, 115,116,126 vcc 16,17,25,39,40,51, 52,66,85,95,103, 109,113,124,128 www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 15 99/10/26 - 8306 pin description rmii interface symbol type pin no description txe[a:f] o 7,13,24,58, 68,76 transmit enable. the RTL8306 asserts high to indicate that valid data for transmission is presented on the txd[1:0] txd[0:1][a], txd[0:1][b], txd[0:1][c], txd[0:1][d], txd[0:1][e], txd[0:1][f] o 8,9, 14,15, 26,27, 59,60, 69,70, 77,78 transmit data [1:0]. crsdv[a:f] i 10,18,28,61, 72,79 crsdv signals. crsdv from phy device is asserted high when media is non-idle. rxd[0:1][a], rxd[0:1][b], rxd[0:1][c], rxd[0:1][d], rxd[0:1][e], rxd[0:1][f] i 11,12, 19,20, 29,31, 62,63, 73,74, 80,81 receive data [1:0]. the RTL8306 captures the receive data on the rising edge of refclk when crsdv is high. refclk i 47 reference clock input. a 50 mhz signal is used for rmii clock reference. mdc o 43 management data clock mdio i/o 44 management data input/output serial eeprom 24c02 interface symbol type pin no description sclk o 121 serial clock: internally pulled high sda i/o 122 serial data input/output: internally pulled high system pins symbol type pin no description rst# i 53 reset: active low to a known reset state. after power-on reset (low to high), the configuration modes from mode pins are determined, the content of serial eeprom is auto- loaded into and the RTL8306 begins to access the management data of phy devices. sysclk i 119 system clock input 50 mhz system clock is used. mode pins (reset-read) symbol type pin no description enloop i 108 enable loop detection: when pulled high upon reset, the auto loop detection is enabled. when pulled low upon reset, it is disabled. encuthr i 117 enable cut-through: pulled high upon reset will select the cut-through mode. pulled low upon reset selects the store-and-forward mode. e nbrdctrl i 107 enable broadcast storm control. www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 16 99/10/26 enfctrl i 112 enable full duplex flow control: pulled high upon reset will enable the full duplex ieee802.3x flow control function. the flow control ability will be write to the management register 4 of phy device one and only one time after power-on reset, for advertising. pulled low upon reset will disable the flow control function. led pin symbol type pin no description loopled# o 54 loop detected led: low active asserted low indicates that a network loop is detected. dramfail o 56 dram fail led: high active asserted high indicates that the embedded dram is failed. test pin symbol type pin no description test i 106 test pin : for internal use must be tied to ground for normal use. power ground pin gnd 6,21,22,23,30,34, 35,36,48,49,64,71, 75,82,83,101,105, 115,116,126, 89,90,91,96,97,98 vcc 16,17,25,39,40,51, 52,66,85,95,103, 109,113,124,128 7. serial eeprom 24c02 format below is the content of serial eeprom 24c02. the content includes configuration, switch ethernet id, crcs for flow control and loop detection. bit byte 7 6 5 4 3 2 1 0 0 0 0 0 0 accepterr 0 0 0 1 0 hashmode 0 0 0 0 0 phyad_rv 2-7 ethernet id (physical address) par47~0 8-11 pause on crc 31~0 12-15 pause off crc 31~0 16-19 loop detection crc 31~0 hashmode: when 0 when 1, address hashing algorithm used for search and learning when 1 when 0, address direct mapping algorithm used accepterr: when 0, crc error packet will be discarded for normal use. when 1, crc error packet can be accepted and forwarded for test. phyad_rv : when 0, port [a]~[h] uses phyad = 01000b ~ 01111b to access external phy status. when 1, port [h]~[a] uses phyad = 01000b ~ 01111b. www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 17 99/10/26 the phyad_rv value can be zero or one for rtl8308, but it must be zero for RTL8306. 8. electrical characteristics 8.1 temperature limit ratings: parameter minimum maximum units storage temperature -55 +125 j operating temperature 0 70 j 8.2 dc characteristics supply voltage vcc* = 3.3v +- 5% symbol parameter conditions minimum typical maximum unit s v oh minimum high level output voltage i oh= -8ma 0.9 * vcc vcc v v ol maximum low level output voltage i ol= 8ma 0.1 * vcc v v ih minimum high level input voltage 0.5 * vcc vcc+0.5 v v il maximum low level input voltage -0.5 0.3 * vcc v i in input current v in= v cc or gnd -1.0 1.0 g a i oz tri-state output leakage current v out= v cc or gnd -10 10 g a i cc average operating supply current i out= 0ma, 160 180 ma 8.3 ac characteristics www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 18 99/10/26 8.3.1 reset and clock timing symbol description minimum typical maximum units f clock (sysck) sysclk clock frequency 40 50 66 mhz t1 sysclk clock period 15 20 25 ns t2 rst# low pulse duration 1000 - - ns 8.3.2 rmii timing symbol description minimum typical maximum units t1 refclk clock period - 20 - ns t2 refclk high level width - 10 - ns t3 refclk low level width - 10 - ns t4 txe ,txd to refclk rising setup time 4 - - ns t5 txe ,txd to refclk rising hold time 2 - - ns t6 csrdv ,rxd to refclk rising setup time 4 - - ns t7 crsdv ,rxd to refclk rising hold time 2 - - ns vdd sysclk rst# t1 t2 reset and clock timing tx data refclk txe txd[1:0] rmii transmit timing t3 t5 t2 t4 t1 www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 19 99/10/26 rx data refclk crsdv rxd[1:0] rmii receive timing t1 t3 t7 t6 t2 8.3.3 phy management timing symbol description minimum typical maximum units t1 mdc clock period - sysck * 32 - ns t2 mdc high level width - sysck * 16 - ns t3 mdc low level width - sysck * 16 - ns t4 mdio to mdc rising setup time (write bits) 10 - - ns t5 mdio to mdc rising hold time (write bits) 10 - - ns t6 mdc to mdio delay (read bits) - - 20 ns data mdc mdio mdio write timing t4 t1 t2 t3 t5 www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 20 99/10/26 data mdc mdio mdio read timing t1 t6 t3 t2 8.3.4 serial eeprom 24c02 timing symbol description minimum typical maximum units f clock (eesck) clock frequency , sclk - - 66 khz t1 clock pulse period 23 - - us t2 delay time, form sclk rising to sda falling 5 - - us t3 delay time, form sda falling to sclk falling 5 - - us t4 delay time, form sclk falling to sda changing 0 - - us t5 delay time, form sda valid output to sclk rising 0 - - us t6 stop set-up time 5 - - us t7 time the bus must is free before a new transmission starting 5 - - us t8 delay time, form sclk falling to sda valid 0 - - us t9 delay time, form sclk falling to sda changing 0 - - us t10 delay time, from sda valid input to sclk rising 10 - - us valid sclk sda (output) sda (input) valid valid valid eeprom interface timing t2 t1 t3 t2 t4 t5 t8 t9 t6 t7 t10 www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 21 99/10/26 9. mechanical information symbol dimension in inch dimension in mm 1. dimension d & e do not include interlead flash. min type max min type max 2. dimension b does not include dambar rotrusion/intrusion. a ?e 0.134 ?e ?e 3.40 3. controlling dimension : millimeter a1 0.004 0.010 0.036 0.10 0.25 0.91 4. general appearance spec. should be based on final visual a2 0.102 0.112 0.122 2.60 2.85 3.10 inspection spec. b 0.005 0.009 0.013 0.12 0.22 0.32 c 0.002 0.006 0.010 0.05 0.15 0.25 d 0.541 0.551 0.561 13.75 14.00 14.25 title : 128 qfp (14x20 mm ) package outline e 0.778 0.787 0.797 19.75 20.00 20.25 -cu l/f, footprint 3.2 mm e 0.010 0.020 0.030 0.25 0.5 0.75 leadframe material : h d 0.665 0.677 0.689 16.90 17.20 17.50 approve doc. no. 530-ass-p004 h e 0.902 0.913 0.925 22.90 23.20 23.50 version 1 l 0.027 0.035 0.043 0.68 0.88 1.08 page of l 1 0.053 0.063 0.073 1.35 1.60 1.85 check dwg no. q128 - 1 y ?e ?e 0.004 ?e ?e 0.10 date oct. 08 1998 c 0 x ?e 12 x 0 x ?e 12 x realtek semi-conductor co., ltd www.datasheet.co.kr datasheet pdf - http://www..net/
8308/8306 preliminary product specification subject to change 22 99/10/26 www.datasheet.co.kr datasheet pdf - http://www..net/

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